Electrical connections within substrates

ABSTRACT

A substrate having a conductive plane and a via passing through the conductive plane is provided. The conductive plane contacts the via to electrically interconnect the via and the conductive plane. A gap in the conductive plane separates a surface of the via from the conductive plane to provide an uninterrupted path for electrical current flowing substantially on the surface of the via.

TECHNICAL FIELD

[0001] The present invention relates generally to the field ofelectronics and, in particular, to electrical connections in substrates.

BACKGROUND

[0002] Situations frequently arise when electronic components, such ascapacitors, integrated circuits, diodes, inductors, or the like,disposed on opposite sides of a substrate, such as a circuit board,microchip, or the like, are electrically interconnected by a conductor,such as a via, disposed within the substrate. The via usually passesthrough one or more electrically conductive planes disposed within thesubstrate and makes direct contact with the electrically conductiveplanes so that the via and electrically conductive planes areelectrically connected.

[0003] One example involves a method for reducing a noise voltage on anoutput impedance of a power source used to power an integrated circuit(IC). The noise voltage is usually the result of a high-frequencycurrent caused by behavior of the IC that gets passed from the IC to thepower source. The noise voltage normally gets superimposed on voltagessupplied by the power source to the IC. This adversely affects theperformance of the IC.

[0004] The method reduces this noise by reducing the output impedance bydirecting the high-frequency current to ground through a capacitorconnected in close proximity to the IC rather than allowing thehigh-frequency current to pass to the power source. In oneimplementation of this method, the capacitor and IC are located onopposite sides of a circuit board, and power and ground connections ofthe IC are connected to the capacitor using vias that pass through thecircuit board. The vias connected to the ground and power connectionsare normally respectively connected to conductive ground and powerplanes disposed within the circuit board between the IC and capacitor.

[0005] It is known to those skilled in the art that high-frequencycurrent flows substantially on the surface of a conductor and does notpenetrate substantially into the interior of the conductor. Therefore,when high-frequency current flows from an electronic component on oneside of a substrate, such as the IC in the above example, to anelectronic component on an opposite side of the substrate, such as thecapacitor in the above example, the high-frequency current flowssubstantially on the surface of the via. However, when thehigh-frequency current encounters the location where the via isconnected to a conductive plane, such as the power plane in the aboveexample, the high-frequency current changes its course so that thehigh-frequency current flows substantially on a surface of the plane.This is because the direct contact between the via and the plane at thislocation forms a solid boundary between the via and the plane that thehigh-frequency current cannot flow through. Therefore, thehigh-frequency current is forced to change its course a number of timesto flow around the conductive plane and back to the via. This occurseach time the high-frequency current encounters a location where the viais connected to a conductive plane and thus causes the high-frequencycurrent to follow an elongated, meandering path as it flows between theelectronic components. One problem with this is the elongated,meandering path presents an inductance between the electroniccomponents, and a noise voltage gets produced on impedance of theinductance as the high-frequency current flows between the electroniccomponents.

[0006] For the reasons stated above, and for other reasons stated belowthat will become apparent to those skilled in the art upon reading andunderstanding the present specification, there is a need in the art forreducing the impedance between electronic components disposed onopposite sides of a substrate that are electrically interconnected by aconductor passing through one or more electrically conductive planesdisposed within the substrate.

SUMMARY

[0007] The above-mentioned problems with impedance between electroniccomponents disposed on opposite sides of a substrate that areelectrically interconnected by a conductor passing through one or moreelectrically conductive planes disposed within the substrate and otherproblems are addressed by embodiments of the present invention and willbe understood by reading and studying the following specification.

[0008] In one embodiment, a substrate having a conductive plane and avia passing through the conductive plane is provided. The conductiveplane contacts the via to electrically interconnect the via and theconductive plane. A gap in the conductive plane separates a surface ofthe via from the conductive plane to provide an uninterrupted path forelectrical current flowing substantially on the surface of the via.

[0009] Further embodiments of the invention include methods andapparatus of varying scope.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010]FIG. 1 illustrates an electronic device according to the teachingsof the present invention.

[0011]FIG. 2 is a perspective view illustrating a connection of a via toa plane according to an embodiment of the present invention.

[0012]FIG. 3 is a top view of FIG. 2.

[0013]FIG. 4 is a perspective view illustrating a connection of a via tomore than one plane according to another embodiment of the presentinvention.

DETAILED DESCRIPTION

[0014] In the following detailed description, reference is made to theaccompanying drawings that form a part hereof, and in which is shown byway of illustration specific illustrative embodiments in which theinvention may be practiced. These embodiments are described insufficient detail to enable those skilled in the art to practice theinvention, and it is to be understood that other embodiments may beutilized and that logical, mechanical and electrical changes may be madewithout departing from the spirit and scope of the present invention.The following detailed description is, therefore, not to be taken in alimiting sense.

[0015] Embodiments of the present invention provide for a high-frequencycurrent flowing substantially on a surface of a via to flow through agap separating the via from a conductive plane through which the viapasses. This reduces inductance and thus impedance and noise as comparedto when a high-frequency current flowing substantially on a surface of avia changes its course and flows substantially on a surface of aconductive plane to flow around the plane.

[0016]FIG. 1 illustrates an electronic device 100 according to anembodiment of the present invention. Electronic device 100 includes asubstrate 101, such as a circuit board, microchip, or the like.Electronic components 102 and 104, such as capacitors, integratedcircuits, diodes, inductors, or the like, are respectively disposed onside 106 and opposite side 108 of substrate 101. Vias 110 ₁ and 110 ₂,e.g., an electrically conductive material, such as copper, aluminum, orthe like, passing through substrate 101 interconnect electroniccomponents 102 and 104. Specifically, via 110 ₁ interconnects a contactpoint 114 ₁ of electronic component 102, e.g., a solder ball, pad, pin,or the like, to a contact point 116 ₁ of electronic component 104.Further, via 110 ₂ interconnects a contact point 114 ₂ of electroniccomponent 102, e.g., a solder ball, pad, pin, or the like, to a contactpoint 116 ₂ of electronic component 104. Conductive planes 122 ₁ to 122_(N) are disposed within substrate 101. In one embodiment, conductiveplanes 122 ₁ to 122 _(N) are substantially parallel to each other. Inanother embodiment, via 110 ₁ is connected to conductive plane 122 _(N).In other embodiments, via 110 ₂ is connected to conductive plane 122 ₁.In some embodiments, conductive planes 122 ₁ to 122 _(N) are groundplanes, power planes, interconnect planes, or the like and are ofcopper, aluminum, or the like.

[0017]FIGS. 2 and 3 illustrate connection of vias 110 to conductiveplanes 122 according to an embodiment of the present invention. FIG. 2is a perspective view and FIG. 3 is a top view of FIG. 2. In oneembodiment, via 110 is an electrically conductive coating of a holepassing through a substrate and thus is a hollow cylinder, as shown inFIGS. 2 and 3.

[0018] Via 10 passes through an aperture 215 passing through conductiveplane 122 to form a gap 230 between a surface 240 of via 10 and asurface 216 of conductive plane 122 corresponding to a perimeter 218 ofaperture 215. In one embodiment, gap 230 is annular, as shown in FIGS. 2and 3. Each of tabs 220 ₁ to 220 _(M) of conductive plane 122 radiateinwardly from perimeter 218 of aperture 215 and span gap 230. Each oftabs 220 ₁ to 220 _(M) of conductive plane 122 respectively contact via110 at locations 222 ₁ to 222 _(M) to electrically connect conductiveplane 122 to via 10. In one embodiment, each of tabs 220 ₁ to 220 _(M)is integral with conductive plane 122. In another embodiment, each oftabs 220 ₁ to 220 _(M) lies substantially in a plane of conductive plane122. Gap 230 provides an uninterrupted path for a portion of ahigh-frequency current flowing substantially on surface 240 of via 110to flow between each of tabs 220 ₁ to 220 _(M), through gap 230, andpast conductive plane 122, as depicted by arrows 250 and 252. Therefore,this portion of the high-frequency current does not change its course asoccurs in conventional situations where there is no gap between the viaand the conductive plane.

[0019] In operation, as depicted in FIG. 1, high-frequency current flowsfrom connection 114 ₁ substantially on surface 240 ₁ of via 110 ₁ to thelocation where via 110 ₁ is connected to conductive plane 122 _(N), asdepicted by arrow 130. As discussed above, gap 230 provides anuninterrupted path for a portion of the high-frequency current to flowas shown by arrow 250 in FIG. 1. This portion of the high-frequencycurrent does not alter its course upon encountering the location wherevia 110 ₁ is connected to conductive plane 122 _(N) to flow on thesurface of conductive plane 122 _(N) as would occur in conventionalsituations where there is no gap between the via and the conductiveplane. Therefore, the inductance and thus the impedance for thehigh-frequency current is lower and it results in lower noise voltagethan for conventional situations where the high-frequency currentchanges its course to flow around the conductive plane.

[0020] The high-frequency current continues to flow substantially onsurface 240 ₁ of via 110 ₁ to connection 116 ₁ of electronic component106, as shown by arrow 133. The high-frequency current flows throughelectronic component 106 from connection 116 ₁ to connection 116 ₂.Then, the high-frequency current flows substantially on surface 240 ₂ ofvia 110 ₂ from connection 116 ₂ to the location where via 110 ₂ isconnected to conductive plane 122 ₁, as shown by arrow 134. As discussedabove, gap 230 provides an uninterrupted path for a portion of thehigh-frequency current to flow as shown by arrow 252 in FIG. 1. Thisportion of the high-frequency current does not alter its course uponencountering the location where via 110 ₂ is connected to conductiveplane 122 ₁ to flow on the surface of conductive plane 122 ₁ as wouldoccur in conventional situations where there is no gap between the viaand the conductive plane. Therefore, the inductance and thus theimpedance for the high-frequency current is lower and it results inlower noise voltage than for conventional situations where thehigh-frequency current changes its course to flow around the conductiveplane. The high-frequency current then continues to flow substantiallyon surface 240 ₂ of via 110 ₂ to connection 114 ₂, as indicated by arrow136.

[0021]FIG. 4 illustrates a via 400 passing through each of conductiveplanes 405 ₁ to 405 _(P) according to another embodiment of the presentinvention. In one embodiment, via 400 and each of conductive planes 405₁ to 405 _(P) are disposed in a substrate, such as substrate 101 ofFIG. 1. In various embodiments, each of conductive planes 405 ₁ to 405_(P) is a ground plane, power plane, interconnect plane, or the like andis of copper, aluminum, or the like. In one embodiment, via 400interconnects electronic components, such as electronic components 102and 104 of FIG. 1, respectively disposed on opposite sides of asubstrate. In another embodiment, via 400 is as described for via 10 ofFIGS. 2 and 3.

[0022] In other embodiments, via 400 is connected to each of conductiveplanes 405 ₁ to 405 _(P) as described above for via 110 and conductiveplane 122 of FIGS. 2 and 3 so that gaps 430 ₁ to 430 _(P) respectivelyseparate a surface 440 of via 400 from conductive planes 405 ₁ to 405_(P) and each of tabs 420 _(1,1) through 420 _(Q,1) to tabs 420 _(1,P)through 420 _(R,P), respectively of each of conductive planes 405 ₁ to405 _(P), respectively span each of gaps 430 ₁ to 430 _(P) toelectrically connect each of conductive planes 405 ₁ to 405 _(P) to via400.

[0023] At least a portion of each of gaps 430 ₁ to 430 _(P) is alignedwith a portion of another of each of gaps 430 ₁ to 430 _(P). Forexample, in one embodiment, a portion of gap 430 ₁ that lies betweensuccessively adjacent tabs of tabs 420 _(1,1) through 420 _(Q,1) ofconductive plane 405 ₁ aligns with a portion of gap 430 _(P) that liesbetween successively adjacent tabs of tabs 420 _(1,P) through 420 _(R,P)of conductive plane 405 _(P). This provides an uninterrupted path for aportion of a high-frequency current flowing substantially on surface 440of via 400 to flow between each of tabs 420 _(1,1) through 420 _(Q,1),through gap 430 ₁, between each of tabs 420 _(1,P) through 420 _(R,P),and through gap 430 _(P) or vice versa, as shown by arrows 450 and 452in FIG. 4.

[0024] To manufacture an electronic circuit board according to anembodiment of the present invention, conductive planes 122 are formedwithin substrate 101. Vias 110 are also formed in substrate 101 so thatthey respectively pass through and make contact with conductive planes122, as illustrated in FIGS. 1-3. In one embodiment, via 400 is formedin a substrate, such as substrate 101, and passes through and makescontact with each of conductive planes 405 ₁ to 405 _(P), as illustratedin FIG. 4.

[0025] A gap 230 is formed between surface 240 of via 110 and conductiveplane 122 to provide an uninterrupted path for current flowingsubstantially on surface 240. In one embodiment, forming gap 230includes forming tabs 220 ₁ to 220 _(M) that span gap 230 and contactsurface 240, as shown in FIGS. 2 and 3. In another embodiment, each ofgaps 430 ₁ to 430 _(P) is respectively formed between each of conductiveplanes 405 ₁ to 405 _(P) and surface 440 of via 400, and a portion ofeach of gaps 430 ₁ to 430 _(P) is aligned with a portion of another ofeach of gaps 430 ₁ to 430 _(P), as shown in FIG. 4. In some embodiments,forming each of gaps 430 ₁ to 430 _(P) includes respectively formingeach of tabs 420 _(1,1) through 420 _(Q,1) to tabs 420 _(1,P) through420 _(R,P), as shown in FIG. 4. cl Conclusion

[0026] Embodiments of the present invention have been described. Theembodiments provide for a high-frequency current flowing substantiallyon a surface of a via to flow through a gap separating the via from aconductive plane through which the via passes. This reduces inductanceand thus impedance and noise as compared to when a high-frequencycurrent flowing substantially on a surface of a via changes its courseand flows substantially on a surface of a conductive plane to flowaround the plane.

[0027] Although specific embodiments have been illustrated and describedin this specification, it will be appreciated by those of ordinary skillin the art that any arrangement that is calculated to achieve the samepurpose may be substituted for the specific embodiment shown. Thisapplication is intended to cover any adaptations or variations of thepresent invention. For example, via 110 of FIGS. 2 and 3 and via 400 ofFIG. 4 can be a solid rather than hollow. Embodiments of the presentinvention are not limited by substrates, such as 101, having two vias,such as 110 ₁ and 110 ₂, as shown in FIG. 1. Rather any number of vias110 may be disposed within substrate 101, and these vias may beelectrically connected to any number of conductive planes, e.g.,conductive planes 122 ₁ to 122 _(N) disposed within the substrate.Moreover, these vias may interconnect any number of electroniccomponents disposed on opposite sides of the substrate. It is manifestlyintended that this invention be limited only by the following claims andequivalents thereof.

What is claimed is:
 1. A substrate comprising: a conductive plane; a viapassing through the conductive plane; wherein the conductive planecontacts the via to electrically interconnect the via and the conductiveplane; and wherein a gap separates a surface of the via from theconductive plane to provide an uninterrupted path for electrical currentflowing substantially on the surface of the via.
 2. The substrate ofclaim 1, wherein the via is adapted to interconnect an electroniccomponent disposable on one side of the substrate and an electroniccomponent disposable on an opposite side of the substrate.
 3. Thesubstrate of claim 1, wherein a tab lying substantially in a plane ofthe conductive plane contacts the via.
 4. The substrate of claim 1,wherein two or more tabs lying substantially in a plane of theconductive plane contact the via.
 5. The substrate of claim 1, whereinthe conductive plane comprises two or more conductive planes and whereinthe gap comprises two or more gaps that respectively separate the two ormore conductive planes from the via.
 6. The substrate of claim 5,wherein a portion of each of the two or more gaps is aligned with aportion of another of each of the two or more gaps.
 7. A substratecomprising: a conductive plane; a via passing through the conductiveplane; wherein a gap separates a surface of the via from the conductiveplane to provide an uninterrupted path for electrical current flowingsubstantially on the surface of the via; and wherein a tab of theconductive plane spans the gap and contacts the via to electricallyinterconnect the via and the conductive plane.
 8. The substrate of claim7, wherein the via is adapted to interconnect an electronic componentdisposable on one side of the substrate and an electronic componentdisposable on an opposite side of the substrate.
 9. The substrate ofclaim 7, wherein the tab comprises two or more tabs.
 10. The substrateof claim 7, wherein the conductive plane comprises two or moreconductive planes and wherein the gap comprises two or more gaps thatrespectively separate the two or more conductive planes from the via.11. The substrate of claim 10, wherein a portion of each of the two ormore gaps is aligned with a portion of another of each of the two ormore gaps.
 12. A substrate comprising: first and second conductiveplanes substantially parallel to each other; first and second viasrespectively passing through the first and second conductive planes,wherein the first and second vias are adapted to interconnect a firstelectronic component disposable on a first side of the substrate and asecond electronic component disposable on a second side of thesubstrate; wherein the first conductive plane contacts the first via toelectrically interconnect the first via and the first conductive planeand the second conductive plane contacts the second via to electricallyinterconnect the second via and the second conductive plane; and whereina first gap separates a surface of the first via from the firstconductive plane to provide an uninterrupted path for electrical currentflowing substantially on the surface of the first via and wherein asecond gap separates a surface of the second via from the secondconductive plane to provide an uninterrupted path for electrical currentflowing substantially on the surface of the second via.
 13. Thesubstrate of claim 12, wherein a tab lying substantially in a plane ofthe first conductive plane contacts the first via.
 14. The substrate ofclaim 13, wherein the tab spans the first gap.
 15. The substrate ofclaim 13, wherein the tab comprises two or more tabs.
 16. The substrateof claim 12, wherein a tab lying substantially in a plane of the secondconductive plane contacts the second via.
 17. The substrate of claim 16,wherein the tab spans the second gap.
 18. The substrate of claim 16,wherein the tab comprises two or more tabs.
 19. The substrate of claim12, wherein the first conductive plane comprises two or more firstconductive planes and wherein the first gap comprises two or more firstgaps that respectively separate the two or more first conductive planesfrom the via.
 20. The substrate of claim 19, wherein a portion of eachof the two or more first gaps is aligned with a portion of another ofeach of the two or more first gaps.
 21. The substrate of claim 12,wherein the second conductive plane comprises two or more secondconductive planes and wherein the second gap comprises two or moresecond gaps that respectively separate the two or more second conductiveplanes from the via.
 22. The substrate of claim 21, wherein a portion ofeach of the two or more second gaps is aligned with a portion of anotherof each of the two or more second gaps.
 23. A method for transmittinghigh-frequency current through a substrate, the method comprising:receiving the high-frequency current at a via passing through aconductive plane disposed within a substrate; and directing thehigh-frequency current along an uninterrupted path substantially on asurface of the via comprising: separating the via from the conductiveplane using a gap, and spanning the gap with one or more tabs of theconductive plane so that the one or more tabs contact the via.
 24. Themethod of claim 23, wherein receiving the current at the via comprisesreceiving the current from an electronic component disposed on thesubstrate.
 25. The method of claim 23, wherein receiving thehigh-frequency current at a via passing through a conductive planedisposed within a substrate comprises receiving the high-frequencycurrent at a via passing through two or more conductive planes disposedwithin the substrate.
 26. The method of claim 25, wherein directing thehigh-frequency current along an uninterrupted path substantially on thesurface of the via comprises: separating the via from each of the two ormore conductive planes respectively using each of two or more gaps;aligning a portion of each of the two or more gaps with a portion ofanother of each of the two or more gaps; and respectively spanning eachof the two or more gaps with one or more tabs of each of the two or moreconductive planes so that the one or more tabs of each of the two ormore conductive planes contact the via.
 27. A method for connecting avia to a conducting plane, the method comprising: passing the viathrough an aperture in the conducting plane such that a gap existsbetween a surface of the via and the conducting plane, wherein the gapprovides an uninterrupted path for electrical current flowingsubstantially on the surface of the via; and spanning the gap with a tabof the conducting plane so that the tab contacts the via.
 28. The methodof claim 27, wherein spanning the gap with a tab comprises spanning thegap with two or more tabs.
 29. A method for manufacturing an electroniccircuit board, the method comprising: forming a conductive plane withina substrate; forming a via within the substrate that passes through theconductive plane and makes contact with the conductive plane; andforming a gap between a surface of the via and the conductive plane,wherein the gap provides an uninterrupted path for current flowingsubstantially on the surface of the via.
 30. The method of claim 29,wherein forming a gap between a surface of the via and the conductiveplane comprises forming a tab that spans the gap and contacts thesurface of the via.
 31. The method of claim 30, wherein forming a tabthat spans the gap and contacts the surface of the via comprises formingtwo or more tabs that span the gap and contact the surface of the via.32. The method of claim 29, wherein forming a conductive plane within asubstrate comprises forming two or more conductive planes within thesubstrate.
 33. The method of claim 32, wherein forming a via within thesubstrate comprises forming two or more vias within the substraterespectively passing through each of the two or more conductive planesand respectively making contact with each of the two or more conductiveplanes.
 34. A method for manufacturing an electronic circuit board, themethod comprising: forming two or more conductive planes within asubstrate; forming a via within the substrate that passes through eachof the two or more conductive planes and makes contact with each of thetwo or more conductive planes; forming each of two or more gapsrespectively between each of the two or more conductive planes and asurface of the via; and aligning a portion of each of the two or moregaps with a portion of another of each of the two or more gaps toprovide an uninterrupted path for current flowing substantially on thesurface of the via.
 35. The method of claim 34, wherein forming each oftwo or more gaps respectively between each of the two or more conductiveplanes and a surface of the via comprises forming a tab spans each ofthe two or more gaps and contacts the surface of the via.
 36. The methodof claim 35, wherein forming a tab that spans each of two or more gapsand contacts the surface of the via comprises forming two or more tabsthat span the gap and contact the surface of the via.